Power Supply Induced Jitter Modeling of an On- Chip Lc Oscillator
نویسندگان
چکیده
With high bandwidth demand in the telecommunication and networking area, low voltage and low jitter Phase Lock Loop (PLL) is becoming of utmost importance. As the data rate becomes faster, the total jitter budget gets smaller. For instance, an OC-192 transceiver compliant is allowed less than 1ps of total jitter due to random noise (rms jitter) and a maximum of 10ps for the deterministic jitter. Therefore, predicting jitter induced both via power supply and random noise using simulation and modeling becomes crucial. In this paper we first discuss the startup condition of an LC VCO oscillator. Next, we briefly touch on the on-chip inductance and varactor structures used in our modeling. Then, we derive a small signal model for the VCO. Finally, we discuss the manner in which the power supply noise gets coupled to the output of the VCO causing power supply induced jitter.
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تاریخ انتشار 2002